Physical Design Technical Leader/Manager

4 days ago

Singapur, Singapore Bitdeer Group Full time

Overview

About Bitdeer: Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan.

Responsibilities
  • Leading the technical execution of logic synthesis and design optimization for compute architectures, including TPUs, NPUs, and custom accelerators.
  • Driving optimization of high-speed arithmetic structures such as MAC arrays, SIMD engines, and systolic arrays for workloads.
  • Providing hands-on expertise in STA, constraint development, and clock tree synthesis (CTS) to meet timing goals across complex multi-clock domains and high-frequency data paths.
  • Applying advanced low-power design techniques (e.g., clock/power gating, dynamic voltage scaling) to reduce energy consumption in chip designs.
  • Defining memory hierarchy strategies (SRAM, DRAM interfaces, cache subsystems) to support performance and efficiency.
  • Collaborating with DFT teams to support scan insertion, MBIST, and JTAG integration while ensuring clean handoff for physical implementation.
  • Partnering closely with physical design teams to resolve congestion, meet timing, and provide physical-aware synthesis and design constraints tailored to architectures (e.g., NoCs, high-speed interconnects).
  • Leading the formal verification and equivalence checking process to ensure functional accuracy between RTL and synthesized netlists.
  • Acting as a technical mentor and go-to expert for synthesis, timing closure, and power optimization, providing guidance and technical reviews across engineering teams.
Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8 years of hands-on experience in ASIC design, with a strong focus on synthesis, STA, and power optimization for complex SoCs.
  • Solid understanding of RTL-to-GDSII flows and hands-on experience with EDA tools such as Synopsys Design Compiler, Cadence Genus, PrimeTime, and Innovus.
  • Expertise in managing multi-clock domain designs, advanced timing closure techniques, and low-power methodologies (e.g., UPF, DVFS).
  • Familiarity with architectures, including NoC design (mesh, torus, AXI), memory optimization (HBM, SRAM), and chiplet-based packaging (2.5D/3D integration).
  • Proficiency in RTL coding (Verilog/SystemVerilog) and scripting (TCL, Python, Perl, Shell) for automation.
  • Strong collaboration and problem-solving skills, with the ability to lead complex technical discussions and resolve design bottlenecks effectively.

Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.

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