Engineer / Senior Engineer (Design Verification)

Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq 1 week ago Be among the first 25 applicants Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq Get AI-powered advice on this job and more exclusive features. Company Overview Ambiq's mission is to enable intelligence everywhere by delivering the lowest power...

Description: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...

About the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire...

Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal...

Responsibilities Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape‑out. Write...

Overview Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts to...

Responsibilities: Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for functionality, performance,...

Department: IC Design & Development Position Summary: Key Responsibilities Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Lead DFT related activities – Scan Insertion, ATPG, Pattern Validation Work with test team in debugging production test issues Help debug & correct any functional...

Job Description: We are seeking a SoC Verification Engineer to test and validate System-on-Chip (SoC)designs. You will work with cross-functional teams to ensure chip functionality through verification using UVM , SystemVerilog , Python , and other cutting-edge tools. Responsibilities: Develop verification plans for module and system-level testing....