(Sr./Staff) Digital Design Verification Engineer

Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq 1 week ago Be among the first 25 applicants Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq Get AI-powered advice on this job and more exclusive features. Company OverviewAmbiq's mission is to enable intelligence everywhere by delivering the lowest...

Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq 1 week ago Be among the first 25 applicants Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq Get AI-powered advice on this job and more exclusive features. Company Overview Ambiq's mission is to enable intelligence everywhere by delivering the lowest...

Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq 1 week ago Be among the first 25 applicants Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq Get AI-powered advice on this job and more exclusive features. Company Overview Ambiq's mission is to enable intelligence everywhere by delivering the lowest...

Job Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Singapore, Central, Singapore **Company Overview**: **Staff Engineer - Design Verification**: **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. -...

**Responsibilities**: - Own verification for various blocks in a SoC, sub-system or an IP and meet coverage goals - Own the test-bench and enable reuse of block level UVM test-benches at sub-system and SOC level - Come up with a comprehensive verification strategy encompassing simulations, formal verification, HW/SW reuse and simulation performance - Work...

**Responsibilities** - Develop detailed verification plans based on design specifications and architectural requirements. - Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology). - Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.Staff Engineer, Design Verification (System Verilog)Responsibilities:You will be responsible for verifying digital and...