Digital Design Verification Engineer

Senior Verification Engineer for Digital IC Design Job Description: We are seeking a highly skilled Senior Verification Engineer to join our team. The ideal candidate will have extensive experience in digital design verification, including SoC and IP block development. The successful candidate will be responsible for developing detailed test plans,...

Verification Engineer We are seeking a skilled Verification Engineer to develop and implement verification environments, tests, and plans for complex digital designs. Develop verification environments and tests to perform functional testing at IP level and SoC level. Design and develop IP level/SoC level test plans based on architectural...

Job Responsibilities: Develop verification plans based on design documents, define module-level verification strategies, build verification environments and frameworks, and complete both module-level and chip-level verification Execute regression testing to improve verification coverage Work with chip design engineers to identify and fix design defects;...

Digital Verification Engineer page is loaded## Digital Verification Engineerlocations: Singapore, Kallangtime type: Full timeposted on: Posted Todaytime left to apply: End Date: February 28, 2026 (30+ days left to apply)job requisition id: R Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has...

JOB DESCRIPTION: - Perform with various activities on RTL design implementation and verification at SoC level. - Responsible for RTL coding, logical synthesis, functional test plan, test bench development, RTL and gate-level simulation/verification, code coverage, formal verification, test vector generation and design documentation. - Work and provide high...

Description: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...

Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and...

Roles & ResponsibilitiesOne of our US Global Semiconductor IC design is growing their design teams in Singapore. Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years. · Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC...

One of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years.Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...

**Design Verification Engineer** Experience : 4+ Years Salary Range :SGD 6500-8500 **Skills Required**: FPGA SoC Verification Skills ASIC SoC Verification Skills System Verilog and UVM Skills Automation Skills. IP Verification Skills Low power UPF based verification skills **Technical Expertise** Languages :Verilog, System Verilog, C,...