Semiconductor Senior GPON Design Verification Engineer

JOB DESCRIPTION: Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts...

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Singapore Semiconductor IoT Application Engineer Responsibilities Define SW design specifications for a complex communications system, in close collaboration with the system development and digital design engineers for power, performance and timing requirements. Provide technical leadership throughout the SW architecture development, working closely with...

One of our US Global Semiconductor IC design is growing their design teams in Singapore. Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years. • Technical Requirements: o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire...

Responsibilities Define verification plans and test cases based on chip design specifications, and establish the verification environment Collaborate with chip design engineers in identifying and fixing design defects and continuously improve verification coverage Participate in gate-level simulation and formal verification Optimize tools and the...

Overview In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Responsibilities Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as...

One of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Lead (DV)Location : SingaporeExperience : 10+ years• Technical Requirements: o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso Knowledge...

Description: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...

About the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...