DFT Engineer

6 days ago


Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations, developing high-quality test vectors, and actively contributing to yield improvement and fault analysis. Responsibilities Lead the design of DFT architecture at the chip level, implementing testing circuits such as Scan, Mbit, Memory repair, and Bscan. Implement DFT circuits and integrate them into the chip, ensuring proper timing constraints for DFT mode convergence. Perform thorough functional verification, pre-simulation, post-simulation, and power simulation of DFT circuits. Troubleshoot and resolve issues effectively. Develop high-coverage, low-cost test vectors and validate them rigorously through simulation and timing analysis. Drive yield improvement efforts and lead fault analysis activities. Take ownership of testing SDC constraint files in testing modes and contribute significantly to timing and power convergence in the backend. Qualifications Bachelor’s degree in Electronics Engineering, Computer Science, or a related field. Advanced degrees (Master’s or Ph.D.) are a plus. Minimum of 7-8 years of experience in DFT, with proven expertise in chip-level DFT architecture design, circuit insertion, and testing. Proficiency in DFT methodologies, including Scan, Mbit, Memory repair, and Bscan. Strong experience with functional verification and simulations (pre/post, power simulation). Demonstrated ability to develop efficient test vectors and perform thorough timing and simulation analysis. Familiarity with yield improvement and fault analysis processes. Experience with DFT tools and scripting languages (e.g., TCL, Perl, Python). Strong problem-solving skills, meticulous attention to detail, and the ability to collaborate effectively with cross-functional teams. #J-18808-Ljbffr


  • DFT Engineer

    2 weeks ago


    Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time $120,000 - $200,000 per year

    Job Overview:We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive...

  • Senior Dft Engineer

    2 weeks ago


    Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time

    **Key Responsibilities**: - **DFT Architecture Design**:Lead the design of DFT architecture at the chip level, implementing testing circuits such as Scan, Mbit, Memory repair, and Bscan. - **DFT Circuit Design and Insertion**:Implement DFT circuits and integrate them into the chip, ensuring proper timing constraints for DFT mode convergence. - **Functional...


  • Singapore OVT group Full time

    Position Overview We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation, ensuring the...

  • Staff Engineer, Dft

    6 days ago


    Singapore AMBIQ MICRO SINGAPORE PRIVATE LTD. Full time

    **Company Overview** Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub - and near-threshold technologies. With increased power requirements of artificial intelligence (AI)...

  • DFT Engineer

    2 weeks ago


    Singapore VOICE THE WAY PTE. LTD. Full time

    Job Description Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis; Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results; Research and evaluate state-of-the-art DFT architectures and methodologies...


  • Singapore Qingdao Global Golden Bridge Enterprise Management Co.,LTD. Full time

    DFT Design Engineer **Salary**: 20-35kRMB / month **Responsibilities**: 1. Design the DFT scheme reasonably according to the requirements; 2. Use the Mentor/Synopsys tool to insert the DFT circuit (JTAG/BSCAN/SCAN/MBIST/ LBIST, etc.); 3. Conduct relevant verification of DFT circuit (ATPG/ BIST simulation /IP verification /Formality); 4. DFT circuit timing...


  • Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time

    Job Overview We are seeking a motivated and detail-oriented Junior AI Chip DFT (Design for Test) Engineer to contribute to the testability of our innovative AI chip designs. This role will involve learning and assisting in the implementation of DFT architectures, integrating test circuits (Scan, Mbit, Memory repair, Bscan), performing simulations, and...


  • Singapore ByteDance Full time

    Description Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications...


  • Singapore ByteDance Full time

    Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications Minimum...


  • Singapore Alpsoft Technologies Pte. Ltd. Full time $90,000 - $120,000 per year

    Responsibilities:DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BISTAnalysis to improve the testability of Digital design at Block and chip level.Implementation of DFT logics for Digital and Mixed Signal IP.Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.Perform ATPG verification and simulation...