Junior AI Chip DFT Engineer

Roles & ResponsibilitiesJob Overview: We are seeking a motivated and detail-oriented Junior AI Chip DFT (Design for Test) Engineer to contribute to the testability of our innovative AI chip designs. This role will involve learning and assisting in the implementation of DFT architectures, integrating test circuits (Scan, Mbit, Memory repair, Bscan),...

Roles & ResponsibilitiesJob Overview: We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan),...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive...

**About the role** This is an exciting opportunity to join AMLOGIC SINGAPORE PTE LTD as a Backend Engineer - DFT/Synthesis/STA. As a full-time employee, you will be based at our office in International Business Park West Region. This role is critical in ensuring the successful delivery of our engineering projects within the Electrical/Electronic Engineering...

**Design-for-Test (DFT) Engineer - Singapore** - Singapore Regular - R&D - Hardware Job ID: A121322 **Responsibilities** Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability...

**Responsibilities**: - Implement DFT including: at-speed scan, LBIST, MBIST, JTAG, self-test, and IP integration - Work closely with synthesis, static timing, and layout engineers to optimize DFT circuits. - Generate and verify Test vectors before chip tapeout. - Support test vector bring up and debug on ATE. - Support silicon failure analysis,...

JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption. Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for...

**Key Responsibilities**: - Work closely with design team and make sure DFT structures are correctly inserted. - Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs. - Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model -...

Job Overview We are seeking an experienced Senior AI Chip Architecture Engineer to lead the development and optimization of cutting-edge AI chip hardware systems. About the Role This strategic thinker will play a pivotal role in defining chip architecture, designing simulators, optimizing performance at various levels, and driving innovation in AI...

Roles & ResponsibilitiesResponsibilities:DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST Analysis to improve the testability of Digital design at Block and chip level. Implementation of DFT logics for Digital and Mixed Signal IP. Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern. Perform ATPG...