Senior / DFT Engineer

**Key Responsibilities**: - Work closely with design team and make sure DFT structures are correctly inserted. - Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs. - Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model -...

Roles & ResponsibilitiesJob Overview: We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan),...

**Responsibilities**: - Implement DFT including: at-speed scan, LBIST, MBIST, JTAG, self-test, and IP integration - Work closely with synthesis, static timing, and layout engineers to optimize DFT circuits. - Generate and verify Test vectors before chip tapeout. - Support test vector bring up and debug on ATE. - Support silicon failure analysis,...

JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption. Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive...

Roles & ResponsibilitiesResponsibilities:DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST Analysis to improve the testability of Digital design at Block and chip level. Implementation of DFT logics for Digital and Mixed Signal IP. Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern. Perform ATPG...

Responsibilities Responsible for DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related Timing/Power-IR problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. ...

Responsibilities: DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST Analysis to improve the testability of Digital design at Block and chip level. Implementation of DFT logics for Digital and Mixed Signal IP. Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern. Perform ATPG verification and...

Job Overview We are seeking a motivated and detail-oriented Junior AI Chip DFT (Design for Test) Engineer to contribute to the testability of our innovative AI chip designs. This role will involve learning and assisting in the implementation of DFT architectures, integrating test circuits (Scan, Mbit, Memory repair, Bscan), performing simulations, and...

**Company Overview** Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub - and near-threshold technologies. With increased power requirements of artificial intelligence (AI)...