Dft Design Engineer/dft设计工程师

**Location**:China, occasional travel to India required Monthly Salary Range (SGD): $4,500 -

Job Overview:We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive...

Job Description Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis; Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results; Research and evaluate state-of-the-art DFT architectures and methodologies...

**Key Responsibilities**: - **DFT Architecture Design**:Lead the design of DFT architecture at the chip level, implementing testing circuits such as Scan, Mbit, Memory repair, and Bscan. - **DFT Circuit Design and Insertion**:Implement DFT circuits and integrate them into the chip, ensuring proper timing constraints for DFT mode convergence. - **Functional...

Position Overview We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation, ensuring the...

Description Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications...

职位名称 AI工程师(欢迎应届毕业生)公司简介

Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications Minimum...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations,...

**Company Overview** Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub - and near-threshold technologies. With increased power requirements of artificial intelligence (AI)...