DFT Engineer

5 years exp **Roles & Responsibilities** Working Hours : 9AM - 6PM Working days : 5 Days Salary : 7500 - 8500 ( Depending on experience ) **Responsibilities**: - Define SoC DfT architecture and DfM concept - Implement and verify DfT measures to meet product specifications and production requirements - Work closely with cross-function teams (design,...

Position Overview We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation, ensuring the...

Position Overview We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation, ensuring the...

**Company Overview** Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub - and near-threshold technologies. With increased power requirements of artificial intelligence (AI)...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations,...

**Specific Responsibilities** - Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools. - Develop and implement low-power DFT architecture and infrastructure. - Generate structural test vectors, analyze and improve coverage, test time and test cost. - Perform pre/post-layout...

Job Description Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis; Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results; Research and evaluate state-of-the-art DFT architectures and methodologies...

DFT Design Engineer **Salary**: 20-35kRMB / month **Responsibilities**: 1. Design the DFT scheme reasonably according to the requirements; 2. Use the Mentor/Synopsys tool to insert the DFT circuit (JTAG/BSCAN/SCAN/MBIST/ LBIST, etc.); 3. Conduct relevant verification of DFT circuit (ATPG/ BIST simulation /IP verification /Formality); 4. DFT circuit timing...

**Responsibilities**: - DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST - Analysis to improve the testability of Digital design at Block and chip level. - Implementation of DFT logics for Digital and Mixed Signal IP. - Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern. - Perform ATPG verification and...

**About Bitdeer**: Bitdeer Technologies Group (Nasdaq: BTDR) is a leader in the blockchain and high-performance computing industry. It is one of the world's largest holders of proprietary hash rate and suppliers of hash rate. Bitdeer is committed to providing comprehensive computing solutions for its customers. The company was founded by Jihan Wu, an early...