Senior SOC/IP Verification Engineer, SystemVerilog/UVM

Job Description: We are seeking a SoC Verification Engineer to test and validate System-on-Chip (SoC)designs. You will work with cross-functional teams to ensure chip functionality through verification using UVM , SystemVerilog , Python , and other cutting-edge tools. Responsibilities: Develop verification plans for module and system-level testing....

A leading technology firm in Singapore is seeking a verification engineer to develop and review test plans for IC design. The ideal candidate will have a degree in Electrical/Electronics/Computer Engineering and at least 1 year of experience in Silicon/IP verification using SystemVerilog/UVM. Strong communication and analytical skills are essential. This...

**SOC / IP Verification Engineer -Singapore** - Singapore Regular - R&D Job ID: A105173A **Responsibilities** **Qualifications** Minimum Qualifications 1. Bachelor's degree or above in microelectronics, computer science or related majors. 2. 3+ years of verification experience, with tape-out experience preferred. 3. Familiar with chip...

**Key Responsibilities**: - Develop and implement comprehensive verification plans for IP and SoC levels. - Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology). - Create directed and constrained-random tests to identify design bugs. - Develop functional coverage and assertion checks to ensure...

Key Responsibilities: Develop and implement comprehensive verification plans for IP and SoC levels. Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology). Create directed and constrained-random tests to identify design bugs. Develop functional coverage and assertion checks to ensure verification...

Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and...

Responsibilities Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and directed...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus, checkers,...

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus, checkers,...