Semiconductor Design Verification Engineer

Our client is one of the world's leading MNC in the Semiconductor industry. With increasing operational expansion in Asia Pacific, my client is now looking for a talented and strong person to fill this role. This is a contract position (12 months contract + 1 month completion bonus)based in Singapore . The role works within the digital team in Singapore that...

Our client is one of the world's leading MNC in the Semiconductor industry. With increasing operational expansion in Asia Pacific, my client is now looking for a talented and strong person to fill this role. This is a contract position (12 months contract + 1 month completion bonus) based in Singapore . The role works within the digital team in Singapore...

**Company Overview**: Ambiq has been on a singular mission since 2010 to put intelligence everywhere by creating the most energy-efficient semiconductor solutions for IoT endpoint devices. Using the revolutionary Subthreshold Power Optimized Technology (SPOT®) Platform, Ambiq's record-breaking ultra-low power solutions, including MCU and SoCs, have helped...

Job Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...

**Design Verification(DV) Engineers: 5+ years**: **Multiple Positions**: **Preferred Locations**: **Singapore**: - Location is not a limiting factor for highly self-motivated and pro-active engineers, who are passionate to build up their career with Marquee. **- We’re looking for highly motivated, SoC Verification Engineers who are responsible to ensure...

Responsibilities Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape‐out. Write...

Responsibilities Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape‑out. Write...

About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’...

**Our vision is to transform how the world uses information to enrich life for all.** Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it...

**Job Summary**: Based in our Singapore office, you will join our IC Lab team as a Verification Engineer. In this role, you will develop and implement advanced verification methodologies, including UVM, SystemVerilog, and SVA, for cutting-edge projects. You will also work with platforms like Palladium Z1, HAPS, and Zebu to deliver high-quality verification...