Design Verification Engineer

Responsibilities Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically...

Job Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...

Description: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...

Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq 1 week ago Be among the first 25 applicants Join to apply for the Sr. Staff Engineer, Design Verification role at Ambiq Get AI-powered advice on this job and more exclusive features. Company Overview Ambiq's mission is to enable intelligence everywhere by delivering the lowest power...

Description Responsibilities You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications. Specific responsibilities include: The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...

**Job Descriptions** - Develop and Review Test Plan based on IC design specification - Develop constrained-Random verification environment for complex DUT - Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance - Implement coverage matrix using cover point and assertion - Create and...

Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal...