Design Verification Engineer
2 weeks ago
Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels. Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out. Collaborate with design engineers to troubleshoot and resolve simulation issues. Provide support to test engineers during post-silicon validation. Mentor and guide team members and junior engineers, aiming to enhance verification efficiency. Requirements: Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience. Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology. Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs. Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores. Experience in verifying designs at RTL and post-P&R gate levels. __________________________________________________________ HOW TO APPLY : Interested candidates, please submit your resume by clicking on “Quick Apply” or contact for more details. Please provide following information in the resume for immediate processing 1) Reasons for leaving current and/or last employment 2) Last drawn and/or current salary 3) Expected salary 4) Date of availability and/or Notice Period All applications will be treated in strictest confidence and only shortlisted candidates will be notified Wee Wai Dan EA License No : 03C5391 EA Reg No : R #J-18808-Ljbffr
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Design Verification Engineer
3 days ago
Singapore NUWAY CFR PTE. LTD. Full time $90,000 - $120,000 per yearOne of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years.Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...
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Design Verification Manager
6 days ago
Singapore OMNIVISION Full timeResponsibilities Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically...
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Design Verification Engineer
4 days ago
Singapore tekskills Full timeYour Job Scope - Block and IP Verification - Block level verification to validate block performance and adherence to requirements - Generate and execute verification plan based on specifications - Architect and implement testbenches using UVM-based constrained-random and formal methods - Coverage definition, implementation, and analysis - Formal Verification...
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(Sr./Staff) Design Verification Engineer
2 days ago
Singapore OmniVision Technologies Singapore Pte. Ltd. Full timeAbout the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...
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(Sr./Staff) Design Verification Engineer
6 days ago
Singapore OMNIVISION Full timeJob Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...
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Verification Engineer
2 days ago
Singapore CHIPGLOBE ASIA PACIFIC PTE. LTD. Full timeJOB DESCRIPTION: - Perform with various activities on RTL design implementation and verification at SoC level. - Responsible for RTL coding, logical synthesis, functional test plan, test bench development, RTL and gate-level simulation/verification, code coverage, formal verification, test vector generation and design documentation. - Work and provide high...
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Senior Engineer
4 days ago
Singapore Future Technology Devices International Ltd Full timeDigital IC Design Verification Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with test team in debugging production test issues Help debug & correct any functional issues found in taped-out devices Participate in...
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Sr. Staff Engineer, Design Verification
2 weeks ago
Singapore Ambiq Full time**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...
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Sr. Staff Engineer, Design Verification
2 weeks ago
Central Singapore Ambiq Micro Full time**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...
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Sr/ IC Design Engineer
2 days ago
Singapore ETHOS TECH ONE PTE. LTD. Full timeOverview Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests for DUT...