Design Verification
4 days ago
ResponsibilitiesYou will be responsible for verifying digital and mixed -signal designs, including systems -on -chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.Specific responsibilities include:The right candidate will be a self -starter who assumes full ownership of DV tasks and delivers high -quality results. Develop test plans at block, sub -system, and chip level.Execute SoC -based verification at full -chip.Write C -based lib packages and tests.Architect and implement scalable and reusable test benches using SystemVerilog and UVM.Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.Automating the test environment for randomized testing and scoreboarding.Utilize advanced debugging techniques to identify and resolve design and verification issues.Perform root -cause analysis and work with design teams to fix identified issuesDefine and track functional and code coverage metrics to ensure thorough verification.Ensure that verification quality meets or exceeds industry standards and project requirements.Edge -based AI inference is preferred. Requirements Requirements RequirementsWhat you need to have to be successfulBSEE /MSEE 5 -8 years Degree of experience in block, sub -system, and full -chip verificationShould have delivered multiple chips functioning to Specification.Identify and manage verification deliverables, milestones, and schedules.Proactively identify potential verification risks and develop mitigation strategies. Collaborate with design, architecture, and software teams to understand and verify design intent.Communicate verification progress, issues, and results to stakeholders and management.Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed -signal designs with low -power design and verification challengesStrong understanding/exposure to Design Verification for low -power battery -operated designs is highly desired.C -based verification in an SoC environment is requiredExperience with ARM processor -based designs and low -power design techniques is a plus.Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl or MakefileTechnologies: ARM M/RISC -V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low -Power
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Design Verification Manager
57 minutes ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeAs a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode...
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Design Verification Manager
1 week ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeAs a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode...
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(Sr./Staff) Design Verification Engineer
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Singapore OMNIVISION Full timeDescription: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...