(Sr.) ISP RTL Design Manager

Join to apply for the (Sr.) ISP RTL Design Manager role at OMNIVISION . Get AI-powered advice on this job and more exclusive features. Responsibilities: Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Define ISP hardware architecture based on product features and performance requirements, including...

Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team Requirements Minimum MSEE, or BSEE, or...

Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Verify logic at ISP level and digital system level. Optimize design for reduced gate count and low power...

Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power...

1 week ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Define ISP hardware architecture based on product features, performance...

Job Responsibilities: Perform IC design development of SerDes IP products Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with Physical designer and RTL designer to achieve timing closure Work with test team in debugging production test issues Help debug & correct any functional...

JOB DESCRIPTION: - Mixed-signal subsystem design from design implementation to final delivery for chip-level integration - Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements - Ensure all required documentation are prepared according to the quality standards - RTL logic design...

Job Responsibilities: Perform IC design development of SerDes IP products Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with Physical designer and RTL designer to achieve timing closure Work with test team in debugging production test issues Help debug & correct any...

JOB DESCRIPTION Mixed-signal subsystem design from design implementation to final delivery for chip-level integration Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements Ensure all required documentation are prepared according to the quality standards RTL logic design of modules...

Responsibilities: Contribute to IP selection and architecture definition; create functional specifications. Perform PPA evaluation and optimization. Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR Support debugging across RTL simulation, gate-level, and post-layout simulations. Conduct...