
ISP RTL Design Engineer
2 days ago
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Responsibilities
- Responsible for implementing ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis).
- Verify logic at ISP level and digital system level.
- Optimize design for reduced gate count and low power consumption.
- Drive ISP design activities in close collaboration with the ISP Algorithm team.
Qualifications
- Minimum MSEE, BSEE, or related/equivalent discipline.
- Experience/knowledge in RTL, C/C++ programming, and verification.
- Strong debugging and problem-solving skills.
- Good communication and interpersonal skills.
- Result-oriented with adaptable behaviors.
- C++/SystemC knowledge with High Level Synthesis experience is a plus.
- Experience/knowledge in CMOS Image Sensors is a plus.
Seniority level
- Entry level
Employment type
- Full-time
Job function
- Semiconductor Manufacturing
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