
(Sr.) ISP RTL Design Manager
2 weeks ago
Join to apply for the (Sr.) ISP RTL Design Manager role at OMNIVISION . Get AI-powered advice on this job and more exclusive features. Responsibilities: Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Define ISP hardware architecture based on product features and performance requirements, including gate count and power estimation. Verify logic at ISP level and digital system level. Optimize design for reduced gate count and low power consumption. Drive ISP design activities in collaboration with ISP Algorithm Team, ISP Design leaders across sites, and Digital System Design Team. Lead, supervise, and mentor a team of RTL design engineers. Requirements: Minimum MSEE, BSEE, or equivalent, with 7+ years of digital design and verification experience. 3+ years of project management or people management experience. Knowledge in CMOS Image Sensors and image signal processing (ISP). Experience with SystemC/C++, SystemVerilog, and Catapult HLS tool. Strong leadership and collaboration skills. Excellent time management, communication, and interpersonal skills. Result-oriented with adaptability to change. Additional Details: Seniority level: Mid-Senior level Employment type: Full-time Job function: Design, Art/Creative, and Information Technology Industry: Semiconductor Manufacturing #J-18808-Ljbffr
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(Sr.) ISP RTL Design Manager
2 weeks ago
Singapore OMNIVISION Full time20 hours ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team Requirements Minimum MSEE, or BSEE, or...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION Full timeGet AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Verify logic at ISP level and digital system level. Optimize design for reduced gate count and low power...
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(Sr./Staff) ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power...
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(Sr./Staff) ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION Full time1 week ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Define ISP hardware architecture based on product features, performance...
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RTL Designer
2 weeks ago
Singapore CURIOUS TEK PTE. LTD. Full timeJob Responsibilities: Perform IC design development of SerDes IP products Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with Physical designer and RTL designer to achieve timing closure Work with test team in debugging production test issues Help debug & correct any functional...
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Rtl Design Engineer
7 days ago
Singapore AAC TECHNOLOGIES PTE. LTD. Full timeJOB DESCRIPTION: - Mixed-signal subsystem design from design implementation to final delivery for chip-level integration - Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements - Ensure all required documentation are prepared according to the quality standards - RTL logic design...
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Senior RTL Design Engineer
5 days ago
Singapore AAC Technologies Full timeJOB DESCRIPTION Mixed-signal subsystem design from design implementation to final delivery for chip-level integration Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements Ensure all required documentation are prepared according to the quality standards RTL logic design of modules...
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Senior RTL Design Engineer
1 week ago
Singapore CANAAN CREATIVE GLOBAL PTE. LTD. Full timeResponsibilities Contribute to IP selection and architecture definition; create functional specifications. Perform PPA evaluation and optimization. Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR Support debugging across RTL simulation, gate-level, and post-layout simulations. Conduct...
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Senior RTL Design Engineer
2 weeks ago
Singapore CANAAN CREATIVE GLOBAL PTE. LTD. Full timeResponsibilities: Contribute to IP selection and architecture definition; create functional specifications. Perform PPA evaluation and optimization. Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR Support debugging across RTL simulation, gate-level, and post-layout simulations. Conduct...