Junior AI Chip DFT Engineer

Job Overview We are seeking a motivated and detail-oriented Junior AI Chip DFT (Design for Test) Engineer to contribute to the testability of our innovative AI chip designs. This role will involve learning and assisting in the implementation of DFT architectures, integrating test circuits (Scan, Mbit, Memory repair, Bscan), performing simulations, and...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations,...

Overview We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations,...

**Responsibilities**: - DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST - Analysis to improve the testability of Digital design at Block and chip level. - Implementation of DFT logics for Digital and Mixed Signal IP. - Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern. - Perform ATPG verification and...

**About the role** This is an exciting opportunity to join **AMLOGIC SINGAPORE PTE LTD**as a **Senior Backend Engineer - DFT/Synthesis**. As a full-time employee, you will be based at our office in **International Business Park West Region**. This role is critical in ensuring the successful delivery of our engineering projects within the...

Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications Minimum...

Description Responsibilities DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test, etc. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related timing/power/IR problems. Partner with test engineers to bring up test vectors on silicon and ensure successful testing. Qualifications...

Overview We are seeking an experienced and highly skilled Senior AI Chip Architecture Engineer to lead the development and optimization of cutting-edge AI chip hardware systems. This role requires a strategic thinker with at least 8 years of experience in digital circuit design or chip architecture engineering. The ideal candidate will play a pivotal role in...

Responsibilities:DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BISTAnalysis to improve the testability of Digital design at Block and chip level.Implementation of DFT logics for Digital and Mixed Signal IP.Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.Perform ATPG verification and simulation...

We are in search of an Engineer who will be responsible for generating Design for Test (DFT) instruments utilizing advanced Electronic Design Automation (EDA) tools. This role will involve working with various DFT instruments, including Memory Built-In Self-Test (MBIST), On-Chip Clock Controller (OCC), Test Access Port (TAP) controller, Boundary Scan, Logic...