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Digital Systems Architect

2 weeks ago

d jurong jurong island tuas sg beBeeDigital Full time $120,000 - $180,000

ISP RTL Design Engineer

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We are seeking a skilled engineer to implement ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC. The ideal candidate will be responsible for designing and developing innovative digital systems.

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Key Responsibilities:

  • ">
  • Implement ISP algorithm into HW using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis)">
  • Define ISP HW Architecture based on product features and performance requirements">
  • Verify Logic at ISP level and Digital System level">
  • Optimize Design for less gate count and low power consumption">
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Requirements:

  • ">
  • Minimum MSEE or BSEE degree plus 3+ years of experience in digital design and verification related field">
  • Experience/knowledge in CMOS Image Sensor and Image Signal Processing (ISP)">
  • Experience/knowledge in System C/C++, System Verilog, and Catapult HLS tool">
  • Strong debugging and problem-solving skills">
  • Good communication and interpersonal skills">
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