Digital Hardware Architect
1 week ago
ISP RTL Design Manager
Job Description:We are seeking a highly skilled ISP RTL Design Manager to join our team. The successful candidate will be responsible for implementing ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC. They will define the ISP hardware architecture based on product features and performance requirements, estimate gate count and power consumption, verify logic at the ISP level and digital system level, optimize designs for reduced gate count and low power consumption, and drive ISP design activities in collaboration with the ISP algorithm team, design leaders in other sites, and digital system design teams.
The ideal candidate will have a strong background in digital design and verification, with experience in CMOS image sensors and image signal processing (ISP). They will also have expertise in System C/C++, System Verilog, and Catapult HLS tools, as well as excellent leadership and communication skills.
Requirements:- Minimum MSEE or BSEE degree, plus 7+ years of digital design and verification experience
- 3+ years project management/people management experience/skill
- Experience/knowledge in CMOS image sensor and image signal processing (ISP)
- Expertise in System C/C++, System Verilog, and Catapult HLS tools
This is a full-time position offering opportunities for career growth and professional development. The successful candidate will be part of a dynamic team and will have access to cutting-edge technology and tools.
Seniority Level:Mid-Senior level
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