Hardware Architect for Image Signal Processing
4 days ago
Are you a skilled hardware engineer with expertise in implementing complex algorithms into digital systems? Do you have a passion for designing and verifying high-performance hardware architectures?
We are seeking an experienced ISP RTL Design Manager to join our team. As a key member of our engineering department, you will be responsible for defining the hardware architecture of our ISP products, ensuring they meet performance requirements while minimizing power consumption.
Key Responsibilities:
- Implement ISP algorithms into HW using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis)
- Define ISP HW Architecture based on product features and performance requirements, including gate count and power estimation
- Verify Logic at ISP level and Digital System level
- Optimize Design for less gate count and low power consumption
- Drive ISP Design activities in close collaboration with cross-functional teams
- Lead and mentor a team of RTL design engineers
Requirements:
- Minimum MSEE or BSEE, plus 7+ years of Digital Design and verification related experience
- 3+ years project management / people management experience / skill
- Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
- Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool
- Ability to lead teams and collaborate effectively with people in different functions
- Strong time management skills to ensure timely completion of deliverables
- Good communication and interpersonal skills
- Results-oriented and adaptable to changes
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