Senior Design Verification Engineer
4 weeks ago
Company Description
Our client’s mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. They have helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Their goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using their advanced ultra-low power system on chip (SoC) solutions.
Their innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. They value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. They embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. They encourage and nurture an environment for growth and opportunities to work on complex, interesting, and challenging projects that will create a lasting impact. Come join us on our quest for 100 billion devices.
Job Description
They are looking for an experienced Staff Design Verification Engineer to join our dynamic team in Singapore. The ideal candidate will have 8-12 years of experience in the field of semiconductor design verification and a proven track record of success in developing and executing verification plans for complex SoC designs. The Design Verification Engineer will be responsible for the verification of digital and mixed-signal designs, including systems-on-chip with multiple CPUs, and digital signal processors, security hardware, and other logic for IoT applications.
- The ideal candidate should have demonstrated successful design verification tasks at block, sub-system, and full-chip level.
- Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding.
- Utilize UVM to create drivers, monitors, predictors, and scoreboards.
- In-Depth knowledge of SoC architecture with AMBA AXI/AHB/APB, DMA’s,Security, clock, and power-gating techniques is required.
- Responsible for verification of block(s) that includes writing tests, assertionand coverage for a block.
- Create tests to achieve coverage goals while verifying functionality.
- Develop support utilities for verification automation, test bench automation, regression, to improve productivity.
- Develop tests to evaluate power and performance aspects of the design.
- Perform gate-level-simulations and participate in supporting FPGA and Post-silicon bring-up
Requirements
- BSEE/MSEE Degree 8-12 years of experience at block, sub-system and full- chip verification.
- Strong in understanding multiple architectures, integrating 3rd party IP’s/VIP’s, have worked with mixed-signal designs with low-power design and verification challenges.
- Experience with System Verilog simulation required.
- Strong understanding/exposure to Design Verification for low-power batteryoperated designs highly desired.
- C based verification in an SoC environment is required.
- Experience with ARM processor-based designs and low-power designtechniques is a plus.
- Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Makefile
- Technologies: ARM SoC (Preferred), AMBA AXI/AHB/APB, DMA, FlowControl, Serial Devices, QoS
- Preferred technologies: MIPI(CSI/DSI), Crypto, OTP, DSP, Low-Power
Tell employers what skills you have
Hardware
ARM
Documentation Skills
Digital Signal Processors
EDA
UVM
QoS
FPGA
SoC
Python
SystemVerilog
Functional Verification
ASIC
Verilog
VLSI
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