Senior Design Verification Engineer

Roles & ResponsibilitiesCompany DescriptionOur client’s mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. They have helped leading manufacturers worldwide develop products that...

Roles & ResponsibilitiesPosition Overview:As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal...

Roles & ResponsibilitiesPosition Overview:As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal...

In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective components such as stimulus, checkers,...

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition Develop detailed module level and SoC level testplans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...

JOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definitionDevelop detailed module level and SoC level testplans for all the functional features, based on the design spec.Develop ASIC verification environment including all the respective components such as stimulus,...

JOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definitionDevelop detailed module level and SoC level testplans for all the functional features, based on the design spec.Develop ASIC verification environment including all the respective components such as stimulus,...

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition Develop detailed module level and SoC level testplans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...

Roles & ResponsibilitiesJOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective...

Roles & ResponsibilitiesJOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective...

Roles & Responsibilities Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Build reusable testbench, constrained-random/directed test cases, and...

Roles & Responsibilities Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Build reusable testbench, constrained-random/directed test cases, and...

Roles & ResponsibilitiesRole : Design Verification EngineerDuration: 12 Months (extendable /convertible to permanent )Location; Singapore Job Description: Will be working as a member of a cross geographic pre_silicon verification team to verify a next generation FPGA SoC. Will be working with design, architecture team to verify micro-architecture and...

Roles & ResponsibilitiesRole : Design Verification EngineerDuration: 12 Months (extendable /convertible to permanent )Location; Singapore Job Description: Will be working as a member of a cross geographic pre_silicon verification team to verify a next generation FPGA SoC. Will be working with design, architecture team to verify micro-architecture and...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs...

Roles & ResponsibilitiesResponsibilities: Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications Design and develop verification testbenches using industry-standard verification languages and methodologies Write and execute test cases to verify mixed-signal circuits for...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Singapore, Central, SingaporeCompany Overview:Staff Engineer - Design Verification:Responsibilities:Specific Responsibilities: Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. Utilize UVM to create drivers,...