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Sr /IC Design Engineer (Design Verification)
4 weeks ago
Job Descriptions
- Develop and Review Test Plan based on IC design specification
- Develop constrained-Random verification environment for complex DUT
- Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs
- Implement coverage matrix using cover point and assertion
- Create and debug tests for DUT
- Resolve bugs with remote designers
Requirements
- Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
- Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
- Strong understanding of verification process from test plan to coverage completion
- Strong communication and Analytical skills
- Understanding of HDL (Verilog, VHDL)
- Experience with designing with FPGA using Vivado is a plus
Ethos Search Associates Pte. Ltd.
EA Licence No: 13C6655
EA Reg No: R1109557 Rose
Tell employers what skills you have
Invention
Analytical Skills
Digital IC Design
EDA
UVM
RTL Design
IP
FPGA
SoC
SystemVerilog
Flash
Computer Architecture
Functional Verification
ASIC
Debugging
IC
Verilog
VLSI
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