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Design Verification Engineer
4 weeks ago
Role : Design Verification Engineer
Duration: 12 Months (extendable /convertible to permanent )
Location; Singapore
Job Description:
- Will be working as a member of a cross geographic pre_silicon verification team to verify a next generation FPGA SoC.
- Will be working with design, architecture team to verify micro-architecture and design across multiple platforms
- Job responsibilities will include plan development, test bench implementation , test case creation and coverage closure;
- Will be responsible for regression, verification infrastructure development
Job Requirements:
- Bachelor's Degree or Master in relevant field
- 4-5 years of relevant experience in Design Verification
- Must have experience in Verilog/System Verilog
- Experience building Liberty files
- Experience in scripting languages like Perl/Python, System verilog and UVM programming experience
Tell employers what skills you have
Documentation Skills
Scripting
Semiconductor Manufacturing
Test Cases
EDA
UVM
IP
FPGA
SoC
SystemVerilog
Semiconductor Device
Ethernet
Flash
Functional Verification
ASIC
System Verilog
Verilog
VLSI
Semiconductor technology
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