Analog Chip Design Engineer
2 weeks ago
About the Role
As a Senior AI Analog Chip Design Engineer, you will be a technical leader, driving the design and optimization of complex analog and mixed-signal circuits for our next-generation AI chips. You will leverage your deep expertise to architect innovative solutions, guide the development of high-performance digital standard cell libraries, and provide strategic direction to layout teams. Your extensive experience will be crucial in ensuring successful tape-outs and fostering a culture of technical excellence within the team.
Responsibilities- Lead Analog Innovation: Spearhead the design, simulation, and optimization of sophisticated analog circuits, utilizing advanced tools (Cadence Virtuoso, Spectre, HSPICE) to achieve exceptional performance, power efficiency, and robustness across various operating conditions.
- Drive Digital Library Excellence: Direct the development and characterization of high-performance, low-power digital standard cell libraries, ensuring they meet stringent performance, power, and area targets for AI applications.
- Architect Advanced Cell Solutions: Conceive and implement novel digital standard cell architectures and methodologies to enhance design productivity and address the unique demands of AI workloads.
- Provide Layout Vision: Offer strategic guidance and oversight to layout engineers, ensuring accurate and efficient physical implementations that meet critical performance and reliability specifications in deep sub-micron technologies.
- Technical Leadership & Mentorship: Lead cross-functional teams, mentor junior and mid-level engineers, and promote a collaborative and innovative environment.
- Communication & Collaboration: Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
- Tape-Out Ownership: Take ownership of analog and mixed-signal blocks through the entire tape-out process, ensuring successful delivery.
- Education: Bachelor’s degree in Electronics Engineering, Computer Science, or a related field. Master’s or Ph.D. strongly preferred.
- Experience: Minimally 8-12+ years of progressive and in-depth experience in analog circuit design and digital standard cell development, with a strong track record in deep sub-micron process technologies (12nm and below). Proven leadership in tape-out of complex analog blocks is essential.
- Technical Mastery: Deep and proven expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
- Tool Proficiency: Mastery-level proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and analysis.
- Digital Cell Expertise: Extensive experience in the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
- Deep Sub-Micron Knowledge: Comprehensive understanding of the challenges associated with deep sub-micron design, including advanced layout optimization techniques, power delivery network design, and signal integrity considerations.
- Leadership & Communication: Demonstrated ability to effectively lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.
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