DFT Engineer
2 weeks ago
Job Description:
- Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis;
- Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results;
- Research and evaluate state-of-the-art DFT architectures and methodologies for SoC/IP designs;
- Develop and maintain in-house DFT flows and automation methods, and deploy them across multiple projects;
- Troubleshoot DFT-related issues during design implementation and silicon bring-up phases.
Requirements:
- Master's degree or above in Computer Engineering, Electrical Engineering, or a related field;
- 3–5+ years of working experience in ASIC/SoC development;
- Solid understanding of Verilog and familiarity with front-end design flow;
- Knowledge of DFT concepts and techniques, including scan insertion, MBIST, and boundary scan;
- Proficient in using industry-standard tools such as Synopsys Design Compiler, DFT Compiler, TetraMAX, VCS, or Mentor Tessent;
- Experience with ATPG, MBIST, or diagnosis; experience in yield analysis is a strong plus;
- Skilled in scripting with Makefile, Tcl, Perl, or Python for design automation;
- Strong communication and presentation skills in English, with a passion for test methodologies and innovation.
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