Senior RTL Design Engineer

3 days ago


Singapore Canaan Creative Global Pte. Ltd. Full time $120,000 - $180,000 per year

Responsibilities:

  • Contribute to IP selection and architecture definition; create functional specifications.
  • Perform PPA evaluation and optimization.
  • Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR
  • Support debugging across RTL simulation, gate-level, and post-layout simulations.
  • Conduct quality checks using FE EDA tools such as , CDC, RDC, etc.
  • Take ownership of the full project lifecycle, from architecture to production.

Qualifications:

  • 5+ years of experience in ASIC frontend design.
  • Strong proficiency in Verilog/VHDL.
  • Hands-on experience with logic FE tools (e.g., VCS, Verdi, Spyglass, DC).
  • Experience in Static Timing Analysis is a strong plus.
  • Prefer candidates with experience implementing advanced-process chips.
  • Familiarity with low-power design and power simulation preferred.
  • Proficiency in TCL, Perl, or similar scripting languages is a plus.
  • Prior experience with multiple tape-outs and chip bring-up is preferred.
  • Leadership or management experience is an advantage.


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