Staff Verification Engineer

Looking for a new challenge? We are hiring for a Staff/ Senior Staff Engineer - Chip Verification to execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements. In your new role you will: - Execute **S **oC verification tasks **and work closely with team members **to...

- Meet the Team As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips. **Responsibilities**: - Block and IP Verification- Block-level verification to validate block performance and adherence to requirements-...

**Responsibilities** - Develop detailed verification plans based on design specifications and architectural requirements. - Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology). - Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC...

**Title**:Senior Staff Design Verification Engineer(SoC) **Location**:Singapore **About the role**: Our client is a global Precision Semiconductor Manufacturing business. They are market leaders in the development of ultra-low-power semiconductor solutions globally. The company aims to pushin the boundaries of energy efficiency and enabling a new...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.Staff Engineer, Design Verification (System Verilog)Responsibilities:You will be responsible for verifying digital and...

Roles & Responsibilities Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, Design Verification (System Verilog) Responsibilities: You will be responsible for verifying...

Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal...

**Responsibilities**: - Own verification for various blocks in a SoC, sub-system or an IP and meet coverage goals - Own the test-bench and enable reuse of block level UVM test-benches at sub-system and SOC level - Come up with a comprehensive verification strategy encompassing simulations, formal verification, HW/SW reuse and simulation performance - Work...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Singapore, Central, Singapore **Company Overview**: **Staff Engineer - Design Verification**: **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. -...