Lead Engineer, Design Verification

**Responsibilities** - Develop detailed verification plans based on design specifications and architectural requirements. - Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology). - Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC...

Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. - Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. - Build reusable testbench, constrained-random/directed test cases, and verification associated...

**Job Descriptions** - Develop and Review Test Plan based on IC design specification - Develop constrained-Random verification environment for complex DUT - Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance - Implement coverage matrix using cover point and assertion - Create and...

**Title**:Senior Staff Design Verification Engineer(SoC) **Location**:Singapore **About the role**: Our client is a global Precision Semiconductor Manufacturing business. They are market leaders in the development of ultra-low-power semiconductor solutions globally. The company aims to pushin the boundaries of energy efficiency and enabling a new...

Location- Singapore- Experience- 10- Job Type**Job Description**: **JD **Design **Verification **Team Lead, SoC** Take charge of verification team. Designing & deploy verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Perform test plan reviews...

**Job Descriptions** - Develop and Review Test Plan based on IC design specification - Develop constrained-Random verification environment for complex DUT - Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs - Implement coverage matrix using cover point and assertion - Create and debug tests for DUT - Resolve bugs with remote...

**Job Descriptions** - Develop and Review Test Plan based on IC design specification - Develop constrained-Random verification environment for complex DUT - Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs - Implement coverage matrix using cover point and assertion - Create and debug tests for DUT - Resolve bugs with remote...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Singapore, Central, Singapore **Company Overview**: **Staff Engineer - Design Verification**: **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. -...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Roles & ResponsibilitiesJob DescriptionDevelop verification plans based on design-related documentation, set up the verification environment, and complete verification from module level to system level. Execute regression testing and enhance verification coverage. Collaborate with chip design engineers to identify and resolve design defects. Guide the...

- About the team SOC Verification Lead **Responsibilities**: - Lead a team to complete the pre-silicon verification of an SoC. - Develop and track execution of chip level test plan to meet product requirements and established quality standards. - Execute and maintain chip level verification regressions. Triage and debug failing tests. - Tests will be...

**About the team** You will be part of our IC Lab team based in our Singapore regional HQ office. **How you will stand out**: - Experience in UVM verification methodology - Experience in developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, and system emulation to...

Roles & ResponsibilitiesJob Description:We are seeking a SoC Verification Engineer to test and validate System-on-Chip (SoC) designs. You will work with cross-functional teams to ensure chip functionality through verification using UVM, SystemVerilog, Python, and other cutting-edge tools.Responsibilities:Develop verification plans for module and system-level...

JOBDESCRIPTION:Responsibility for test plans, testbench documentationand implementation. Use SystemVeriloglanguage, SVA and UVM methodology for block levelverification. Debug tests with designengineers to deliver functionally correct design blocks.Close coverage measures to identify verification holesand show progress towards tape-out. Writescripts to...

Roles & ResponsibilitiesOur client is one of the leader in the semicon industry, they are seeking for a Design & Verification Engineer (CPU) to join them on a 12 month contract.Job description: ARM/MIPS-based CPU/DSP IP Configuration, RTL Integration, Verification & IP Management Develop functional verification plan, reusable test bench &...

Job Responsibilities - Responsible for setting up the verification plan - Responsible for setting up the module and SoC verification platform - Responsible for designing test cases according to the test plan - Responsible for checking the function and code coverage - Participate in FPGA prototype verification - Participate in firmware problems debug Job...

**Job Description & Requirements**: - Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level - Develop IP level/SoC level test plans based on the design/architectural specs. - Coverage Analysis and Coding - Run simulations & regressions, debug test failures to identify test case issues & RTL design issues -...

Perform Digital IC Verification and maintain verification environment for module and SOC level using UVM methodology. - Create and debug test cases and Verification IP and write and review verification plan. - Carry out assertion-based verification and code coverage analysis on module and SOC level. **Requirements**: - Degree in Electrical/Electronic...

Looking for a new challenge? We are hiring for a Staff/ Senior Staff Engineer - Chip Verification to execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements. In your new role you will: - Execute **S **oC verification tasks **and work closely with team members **to...