
Senior ISP Design Lead
1 week ago
As a seasoned ISP Design Manager, you will lead a team of talented engineers in designing and implementing cutting-edge Image Signal Processing (ISP) solutions. Your expertise in high-level synthesis, SystemC, SystemVerilog, and Catapult HLS tools will drive the development of innovative hardware architectures that meet our product features and performance requirements.
Key Responsibilities:
- Design and implement ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC.
- Develop and refine ISP hardware architecture based on product features and performance requirements.
- Verify logic at the ISP level and digital system level to ensure seamless integration.
- Optimize designs for reduced gate count and low power consumption.
- Collaborate with cross-functional teams, including algorithm, design, and digital system design teams.
- Lead, supervise, and mentor a team of RTL design engineers.
- Bachelor's or Master's degree in Electrical Engineering or Computer Science, plus 7+ years of experience in digital design and verification.
- 3+ years of project management and people management experience/skill.
- Expertise in CMOS Image Sensor and image signal processing.
- Proficiency in System C/C++, System Verilog, and Catapult HLS tool.
- Excellent leadership and collaboration skills.
- Strong time management skills to deliver projects on time.
- Good communication and interpersonal skills.
- Results-oriented and adaptable to changes.
- Opportunities for career growth and professional development.
- Collaborative and dynamic work environment.
- Recognition and rewards for outstanding performance.
- A chance to work on cutting-edge technologies and contribute to the company's success.
Join Our Team:
We are looking for a highly motivated and experienced ISP Design Manager to join our team. If you have a passion for innovative design, excellent leadership skills, and a proven track record of delivering results, we encourage you to apply for this exciting opportunity.
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Senior ISP Design Lead
2 weeks ago
Singapore beBeeManager Full timeISP Design Manager Job Description As a seasoned ISP Design Manager, you will lead a team of talented engineers in designing and implementing cutting-edge Image Signal Processing (ISP) solutions. Your expertise in high-level synthesis, SystemC, SystemVerilog, and Catapult HLS tools will drive the development of innovative hardware architectures that meet our...
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Senior ISP Architecture Lead
2 weeks ago
Singapore beBeeDesign Full time $120,000 - $180,000The role of ISP Design Manager is crucial in the development of cutting-edge image signal processing technology. As an expert in this field, you will be responsible for overseeing the design and implementation of innovative ISP solutions.In this position, you will lead a team of skilled engineers to develop hardware architecture based on product features and...
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(Sr.) ISP RTL Design Manager
1 week ago
Singapore OMNIVISION Full time20 hours ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION Full time1 week ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Define ISP hardware architecture based on product features, performance...
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(Sr.) ISP RTL Design Manager
3 days ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power...
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ISP RTL Design Engineer
1 week ago
Singapore OMNIVISION Full timeGet AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Verify logic at ISP level and digital system level. Optimize design for reduced gate count and low...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION Full timeGet AI-powered advice on this job and more exclusive features. Direct message the job poster from OMNIVISION Responsibilities Responsible for implementing ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis). Verify logic at ISP level and digital system level. Optimize design for reduced gate count and low power...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...
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ISP RTL Design Engineer
1 week ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team Requirements Minimum...
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ISP RTL Design Engineer
2 weeks ago
Singapore OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. Full timeResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team Requirements Minimum MSEE, or...