Principal Semiconductor Chip Designer

2 weeks ago

Singapore beBeeDesign Full time $200,000 - $250,000
Job Overview

As a Senior Physical Design Engineer, you will lead the development of complex semiconductor chips. Your responsibilities will include optimizing design constraints, performing timing analysis, and applying optimization techniques to achieve block-level timing closure.

Key Responsibilities
  • Develop and implement physical design processes for RTL to GDS implementation.
  • Achieve block-level timing closure by optimizing design constraints and performing timing analysis.
  • Conduct formal checks to ensure designs meet functional and timing requirements.
  • Perform low-power checks and analyze power consumption to optimize power efficiency.
  • Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
  • Execute block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff processes.
  • Utilize Synopsys and Cadence APR tools for high-quality physical design.
  • Develop and employ scripts in Tcl, Perl, or Python to automate design tasks and improve the design flow.
Qualifications/ Requirements
  • Bachelor's/master's degree in electrical engineering, Computer Engineering, or a related field.
  • 3-5 years of experience in physical design for semiconductor chips.
  • Proficiency in RTL-to-GDS flow, timing closure, low-power design, and power analysis.
  • Strong understanding of UPF for power management and control.
  • Experience with block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff.
  • Familiarity with Synopsys and Cadence APR/Sign-off tools.
  • Proficiency in scripting languages such as Tcl, Perl, or Python for automation.

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