Senior Lead Semiconductor Designer

1 week ago

Singapore beBeePhysicalDesign Full time $150,000 - $200,000
Job Description

A skilled Senior Physical Design Engineer will be responsible for the entire process from RTL to GDS, ensuring successful implementation of complex semiconductor chips. They will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation.

Key Responsibilities:

  • Lead the physical design process, overseeing RTL to GDS implementation for semiconductor chips.
  • Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
  • Conduct formal checks to ensure designs meet functional and timing requirements.
  • Perform low-power checks and analyze power consumption to optimize power efficiency.
  • Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
  • Execute block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff processes.
  • Utilize Synopsys and Cadence APR (Automated Routing and Place) tools for high-quality physical design.
  • Develop and employ scripts in Tcl, Perl, or Python to automate design tasks and improve the design flow.
  • Mentor junior engineers and provide technical guidance and support as needed.


Qualifications & Requirements

Seeking a qualified candidate with a degree in electrical engineering, computer engineering, or related field. Requires 3-5 years of experience in physical design for semiconductor chips and proficiency in RTL-to-GDS flow, timing closure, low-power design, and power analysis. Additionally, strong understanding of UPF for power management and control is necessary. Experience with block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), and Formal Verification (FM) signoff is required. Familiarity with Synopsys and Cadence APR/Sign-off tools and scripting languages such as Tcl, Perl, or Python is also desired.

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