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ISP RTL Design Engineer

2 months ago

Singapore BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD. Full time
Design Engineer - ASIC Design

Black Sesame Technologies (Singapore) PTE. LTD. is seeking a highly skilled Design Engineer to join our team. As a key member of our design team, you will be responsible for designing micro-architecture for ISP and CV algorithms, performing RTL design using Verilog/System Verilog and HLS tools, and supporting the analysis of metrics related to power, performance, and area.

Responsibilities:
  • Design and develop micro-architecture for ISP and CV algorithms
  • Perform RTL design using Verilog/System Verilog and HLS tools
  • Analyze and optimize metrics related to power, performance, and area
  • Collaborate with architects and DV Engineers to ensure efficient verification signoff
  • Support FPGA tasks, including emulation, validation, and debugging
Requirements:
  • Master's degree in Electrical/Electronics/Computer Engineering
  • Entry-level position; relevant coursework or project experience in ASIC design or image signal processing is a plus
Technical Skills:
  • Experience/knowledge in Verilog/SystemVerilog and C/C++
  • Familiarity with ASIC design processes and frontend design
  • Knowledge of image/vision/video data processing or algorithm acceleration is beneficial
  • Familiarity with scripting languages (Python, Perl, Tcl) is a plus
Soft Skills:
  • Strong teamwork and communication skills
  • Strong analytical skills and a willingness to learn and adapt in a dynamic environment