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Senior Image Processing RTL Design Engineer
2 months ago
This position involves the implementation of ISP Algorithm into Hardware using Verilog, SystemVerilog and/or SystemC for High Level Synthesis.
Responsibilities- Implementing ISP Algorithm into Hardware using Verilog, SystemVerilog and/or SystemC
- Verify Logic at ISP level and Digital System level
- Optimizing Design for less gate count and low power consumption
- Collaborating with ISP Algorithm Team to drive ISP Design activities
- Minimum MSEE, or BSEE, or related/equivalent discipline
- Experience / knowledge in RTL, C/C++ programming and verification
- Strong debugging and problem-solving skills
- Good communication and interpersonal skills
- Result-oriented and adaptable to change behaviors
- C++/SystemC knowledge with High Level Synthesis experience is a plus
- Experience / knowledge in CMOS Image Sensor is a plus
The estimated salary for this position ranges between SGD 120,000 - SGD 180,000 per annum, depending on qualifications and experience.
About UsAt OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD., we are dedicated to innovation and excellence in the field of image processing and computer vision.
