Lead Engineer, RTL Design

Roles & ResponsibilitiesJob Responsibilities: Perform IC design development of SerDes IP products Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with Physical designer and RTL designer to achieve timing closure Work with test team in debugging production test issues Help debug...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, RTL DesignResponsibilities:We are seeking a talented RTL Engineer to join our team in Singapore. As an...

About the RoleWe are seeking a Senior RTL Design Engineer to join our team in Singapore. This is an exciting opportunity for a talented individual to work alongside a seasoned group of engineers and contribute to the development of innovative solutions.Job DescriptionAs a Senior RTL Design Engineer, you will be responsible for developing and implementing...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team ...

Responsibilities: Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days),...

Responsibilities: Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

Responsibilities:Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...

Responsibilities:Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Roles & ResponsibilitiesCompany OverviewAmbiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks...

ResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team RequirementsMinimum MSEE, or BSEE,...

We are seeking a skilled Senior RTL Design Engineer to join our team at OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.Company OverviewOMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. is a leading provider of image sensor solutions. Our company is dedicated to delivering high-quality products that meet the needs of our customers.About the JobThis is an exciting...

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

As a Senior RTL Architect at SEARCH STAFFING SERVICES PTE. LTD., you will be responsible for leading the design of high-quality digital SOC modules on the MCU.The ideal candidate will possess deep knowledge of current and emerging SOC design technologies, as well as expert-level skills in designing, implementing, and troubleshooting IPs and SOC.You will work...

Job DescriptionREALTEK SINGAPORE PRIVATE LIMITED is seeking a highly skilled Senior ASIC Design Engineer to join our team.Job Summary:We are looking for an experienced ASIC Design Engineer with expertise in designing and developing complex digital ICs. The successful candidate will be responsible for leading the design and development of SoC architectures,...

Roles & ResponsibilitiesThis is an opportunity to be a key player at a company with a great reputation in IoT semiconductor technology and growing business. We are looking for experienced/senior engineers to join our team in Singapore and be involved to develop the next generation IoT/AI chips based on a revolutionary architecture. Work with team to define...

Roles & ResponsibilitiesPosition Overview: The Senior Design Engineer will lead the development of micro-architecture for ISP and CV related algorithms. They will utilize RTL design using Verilog/System Verilog coding and HLS tools like Catapult, and analyze metrics such as power, performance, and area to meet key objectives. They will also drive...

Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the So C design. Establish and manage the infrastructure and environment for automated verification of the So C's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and...

Qualification (s) – BE/ BTech/ MTech/MS/ PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering. Experience – Fresh Graduate Diploma with 0 to 2 years experence including IHL and Singapore Polytechnics Graduate with EEE qualifications. Job Description – RTL coding and module-level verification of digital IC...