RTL Designer

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. RTL Lead EngineerResponsibilities:We are seeking a talented RTL Engineer to join our team in Singapore. As an RTL...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team ...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team ...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, RTL DesignResponsibilities:We are seeking a talented RTL Engineer to join our team in Singapore. As an...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, RTL DesignResponsibilities:We are seeking a talented RTL Engineer to join our team in Singapore. As an...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.RTL Lead EngineerResponsibilities:We are seeking a talented RTL Engineer to join our team in Singapore. As an RTL...

About the RoleWe are seeking a Senior RTL Design Engineer to join our team in Singapore. This is an exciting opportunity for a talented individual to work alongside a seasoned group of engineers and contribute to the development of innovative solutions.Job DescriptionAs a Senior RTL Design Engineer, you will be responsible for developing and implementing...

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, RTL Design Responsibilities: Own and be responsible for pre-tape out quality for digital SOC modules on the MCU. Explore...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the SoC Design Engineering team which will be working on projects. Senior Staff Engineer, RTL Design Responsibilities: We are seeking a talented RTL Engineer to join our team in Singapore. As an RTL Engineer,...

Responsibilities: Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

ResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm Team RequirementsMinimum MSEE, or BSEE,...

Responsibilities: Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

Responsibilities: Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

Roles & ResponsibilitiesResponsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

Responsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding, implementation, and synthesis for...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

Responsibilities:Responsible for implementing ISP Algorithm into HW using Verilog, System Verilog and/or System C (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low...

Responsibilities:Lead RTL design, simulation, and verification for Tetra Mem ASIC/So C products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...