Principal ASIC Design Engineer

3 days ago


Singapore MANPOWER STAFFING SERVICES (SINGAPORE) PTE LTD Full time
Senior Design Engineer Position

We are seeking a highly skilled Principal ASIC Design Engineer to lead the development of micro-architecture for ISP and CV algorithms.

About the Role
  • Leverage your expertise in RTL design using Verilog/System Verilog and HLS tools (Catapult) to drive innovation and efficiency in our projects.
  • Analyze and optimize power, performance, and area to ensure our designs meet the highest standards.
  • Collaborate with architects and DV Engineers to drive verification signoff and lead FPGA tasks including emulation, validation, and debugging.
Requirements
  • A Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering is required.
  • A minimum of 3 years of ASIC design experience is necessary.
  • You should have advanced proficiency in HDL languages and in-depth knowledge of all phases of ASIC frontend design and sign-off.
  • Strong analytical skills and proficiency in scripting languages like Python, Perl, or C/C++ are also essential.
Compensation

The estimated salary for this role is SGD $120,000 - $180,000 per annum, depending on your experience and qualifications. This competitive compensation package reflects the company's commitment to attracting and retaining top talent in the industry.



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