Design Verification Engineer

We are seeking an experienced Design Verification Engineer to join our team in the semiconductor industry. The ideal candidate will have 3+ years of hands-on experience in verification, including writing UVM tests, debugging, and working with industry-standard simulators. You will be responsible for building and executing comprehensive verification...

Roles & ResponsibilitiesDesign Verification EngineerExperience : 6+ YearsSalary Range :SGD 7000-10000Skills Required:FPGA SoC Verification SkillsASIC SoC Verification SkillsSystem Verilog and UVM SkillsAutomation Skills .IP Verification SkillsLow power UPF based verification skillsTechnical ExpertiseLanguages :Verilog, System Verilog, C, C++.Verification...

Roles & ResponsibilitiesDesign Verification EngineerExperience : 6+ YearsSalary Range :SGD 7000-10000Skills Required:FPGA SoC Verification SkillsASIC SoC Verification SkillsSystem Verilog and UVM SkillsAutomation Skills .IP Verification SkillsLow power UPF based verification skillsTechnical ExpertiseLanguages :Verilog, System Verilog, C, C++.Verification...

About This OpportunityEthos Search Associates Pte. Ltd. is seeking an experienced Design Verification Engineer to join our team.Job Description:We are looking for a skilled Design Verification Engineer with a strong background in IC design verification using SystemVerilog and UVM. The successful candidate will be responsible for developing and reviewing test...

Direct message the job poster from EnviroDynamics Solutions Pte Ltd Director at EnviroDynamics Solutions Pte Ltd - Headhunter for Engineering/IT & Healthcare sectors Job Description: As a Senior Verification Engineer, you will play a crucial role in ensuring the quality and reliability of our complex ASIC designs. Your responsibilities will include: Test...

BETA You can view this job in Engineering, Manufacturing, Sciences / Laboratory / R&D Flexi-Hours $8,000 to $12,000 Monthly SEARCH STAFFING SERVICES PTE. LTD. Staff Engineer, Design Verification MCF-2024-1704240PAYA LEBAR SQUARE, 60 PAYA LEBAR ROAD 409051Permanent, Full Time Professional 10 years exp Our client is a leading startup in the semiconductor...

Roles & ResponsibilitiesJOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, Design VerificationResponsibilities:You will be responsible for verifying digital and mixed-signal...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, Design VerificationResponsibilities:You will be responsible for verifying digital and mixed-signal...

ETHOS TECH ONE PTE. LTD. is seeking a highly skilled Senior Verification Engineer to join our team in designing and developing cutting-edge ICs.The ideal candidate will have a strong background in digital IC design, with expertise in silicon/ IP verification using SystemVerilog/UVM. They should possess excellent analytical skills, with the ability to develop...

Description: Responsibilities You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications. Specific responsibilities include: The right candidate will be a self-starter who assumes full ownership of DV tasks...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs...

Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the So C design. Establish and manage the infrastructure and environment for automated verification of the So C's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and...

Job DescriptionWe are seeking an experienced Senior Verification Engineer to join our team in Singapore. The successful candidate will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.Key Responsibilities:Develop test...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Roles & ResponsibilitiesJob description Experience in UVM verification methodology Experience in developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification Disciplined, quality-minded, and ...

Roles & ResponsibilitiesJob description Experience in UVM verification methodology Experience in developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification Disciplined, quality-minded, and ...

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition Develop detailed module level and SoC level testplans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...