Digital Verification Engineer for Power Management ASICs
24 hours ago
Digital Verification Engineer for for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).
* Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.
* Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure.
* Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.
* Work includes debugging of complex embedded systems including SOCs, firmware, embedded sequencers.
* Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target.
Preferred Qualifications
MS+2 Years ASIC design, verification, or related work experience
Strong troubleshooting skills across embedded systems disciplines (digital RTL, Firmware, analog behavioral models)
Strong communication and organizational skills
Strong process-oriented mindset.
Expert-level System Verilog Programming
Advanced UVM/SV (Universal Verification Methodology using System Verilog)
Python or Perl scripting
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
3+ years ASIC design, verification, or related work experience
Tell employers what skills you have
Perl
Analog
Documentation Skills
Scripting
Embedded Systems
Power Management
UVM
Python
Firmware
Telemetry
SystemVerilog
Functional Verification
ASIC
Debugging
Verilog
VLSI
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