Senior ASIC Physical Design Expert
5 days ago
We are seeking a seasoned ASIC Physical Design Engineer to join our team. This role involves implementing complex SoC designs in cutting-edge process technologies.
- Main responsibilities include floor planning, power planning, integrated package and floorplan design, place and route, clock tree synthesis, and timing closure.
- The ideal candidate will plan and execute signal integrity analysis, physical verification (DRC, ERC, LVS), DFM, DFY, and tapeout.
- Innovative flow development is required to meet QoR targets and ensure predictability.
- The selected individual will develop flows to achieve best-in-class power-performance-area (PPA) metrics.
A degree or master's in physical design with at least 8 years of experience in physical design is required.
- Candidates should be proficient in handling netlist-to-GDSII conversion for multiple tape-outs.
- Experience with EDA tools from Synopsys, Cadence, and Mentor, particularly Innovus and Calibre, is essential.
- Hands-on expertise in chip/block floor planning, placement optimizations, CTS, routing, block/top level signoff STA, physical verification, and reliability checks is necessary.
- A strong understanding of physical implementation of timing/functional ECOs is required.
- Proficiency in TCL scripting is expected.
This position is located near Bendemeer MRT station.
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