Senior ASIC Design Specialist
2 weeks ago
We are seeking a highly skilled ASIC Physical Design Engineer to lead our team in the physical implementation of complex SoC designs in cutting-edge process technologies.
Main Responsibilities:
- Implement multimillion gate SoC designs in advanced process nodes (28nm, 16nm, 14nm, 7nm)
- Work on all aspects of physical design including floor planning, power planning, integrated package and floorplan design, place and route, clock plan and tree synthesis
- Plan and implement complex analog IP integration, parasitic extraction, timing closure, power/IR drop, signal integrity analysis, physical verification (DRC, ERC, LVS), DFM and DFY, and tapeout
Key Skills and Qualifications:
- Bachelor's or Master's degree in Electrical Engineering or Computer Science with 8 years or more of experience in physical design
- Handle netlist to GDSII at chip/block level for multiple tapeouts
- Hands-on experience on technology nodes like 28nm, 16nm and below
- Good knowledge of EDA tools from Synopsys, Cadence, and Mentor, particularly experience with Innovus & Calibre is a plus
- Hands-on experience in chip/block floor planning, placement optimizations, CTS and routing, block/top level signoff STA
- Good understanding and experience with physical verification (DRC/LVS/ERC/antenna) and other reliability checks (IR/EM/Xtalk)
- Exposure in physical implementation of timing/functional ECOs
- Proficient in TCL, Perl scripting is a plus
Requirements:
- Develop innovative solutions to meet QoR targets and ensure predictability
- Collaborate with cross-functional teams to drive project success
- Stay up-to-date with industry trends and emerging technologies
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