Senior ASIC Design Verification Engineer

4 days ago

Singapore beBeeVerification Full time $90,000 - $120,000
Job Description:

As a senior engineer in the ASIC Design Verification team, you will be responsible for developing and implementing advanced verification methodologies for IP/SOC designs. Your primary focus will be on creating test plans, developing verification environments/testbenches, and verifying modules/IP/SOCs.

Responsibilities include:
1. Develop and review test plans to ensure thorough verification of IP/SOC designs.
2. Create verification environments/testbenches at the module/IP/SOC level using SystemVerilog/UVM.
3. Implement randomization-based coverage-driven verification methodology and functional/code coverage closure.
4. Work closely with designers to ensure seamless integration of verification IP and reference models into design flows.
5. Troubleshoot issues with UVM, SystemVerilog, Verilog, and SystemC code.
6. Collaborate with peers to implement formal verification techniques and develop automation flow.

Requirements:

To excel in this role, you should possess a strong background in IC/ASIC design verification experience, preferably on SOC, Ethernet, PCIe, DDR, USB, and ARM CPU. A bachelor's degree in EEE/computer/IC design or a related field is required, along with a minimum of 2 years of relevant experience.

Key skills and qualifications include:
1. Strong experience and debugging ability in SystemVerilog/UVM.
2. Proficiency in Synopsys/Cadence/Mentor simulator and debugging flow.
3. Familiarity with UNIX scripting (Python, Perl, makefile Cshell).
4. Ability to learn new technologies quickly.
5. Experience with low-power verification is a plus.

Benefits:

We offer a comprehensive program for professional development/career growth, providing opportunities to work on challenging projects and learn from the best experts in this field. Our team focuses on diversity and inclusiveness, welcoming passionate talents who love new challenges and are eager to learn new technologies.

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