Low Power Design Verification Engineer

About this Verification OpportunityThis position presents a unique chance to contribute to cutting-edge technology in the ultra-low power semiconductor industry, focusing on innovative products that redefine energy efficiency.Key Responsibilities:Develop detailed verification plans based on design specifications and architectural requirements.Create and...

Low-Power Design EngineerWe are seeking an experienced Low-Power Design Engineer to join our team. This is a unique opportunity to work on cutting-edge projects and develop innovative solutions.As a Low-Power Design Engineer, you will be responsible for designing and implementing low-power digital circuits, including scan insertion, boundary scan, MBIST,...

**Responsibilities** - Develop detailed verification plans based on design specifications and architectural requirements. - Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology). - Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Singapore, Central, Singapore **Company Overview**: **Staff Engineer - Design Verification**: **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. -...

**Company Overview **Responsibilities **Specific responsibilities include**: - Develop test plans at block, sub-system, and chip level. - Execute SoC-based verification at full-chip. - Write C-based lib packages and tests. - Architect and implement scalable and reusable test benches using SystemVerilog and UVM. - Develop comprehensive test cases, stimulus...

Description: **Responsibilities** **Specific responsibilities include**: - Develop test plans at block, sub-system, and chip level. - Execute SoC-based verification at full-chip. - Write C-based lib packages and tests. - Architect and implement scalable and reusable test benches using SystemVerilog and UVM. - Develop comprehensive test cases, stimulus...

Roles & ResponsibilitiesOur client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects.Staff Engineer, Design Verification (System Verilog)Responsibilities:You will be responsible for verifying digital and...

Roles & Responsibilities Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Staff Engineer, Design Verification (System Verilog) Responsibilities: You will be responsible for verifying...