Low Power Design Engineer
1 week ago
We are seeking an experienced Low-Power Design Engineer to join our team. This is a unique opportunity to work on cutting-edge projects and develop innovative solutions.
As a Low-Power Design Engineer, you will be responsible for designing and implementing low-power digital circuits, including scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
The successful candidate will have a strong background in digital design, with experience in creating and implementing hierarchical DFT architecture in complex SoC. They will also have extensive knowledge of timing concepts and constraint development, as well as experience in working with test engineering teams to bring up production test programs.
Key qualifications include:
- BS/MS in ECE/EE
- At least 10 years of experience in DFT implementation
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST
- Experience in creating and implementing hierarchical DFT architecture in complex SoC
- Experience in Low-Power DFT and MBIST
- Experience in test time and test coverage analysis for scan and MBIST patterns
Additional requirements include strong verbal and written English communication skills, motivation, self-driven attitude, attention to detail, and ability to work collaboratively as part of a cross-functional team.
Benefits of joining our team include the opportunity to work on exciting and challenging projects, professional growth and development, and a dynamic and supportive work environment.
We offer competitive compensation and benefits packages, as well as opportunities for career advancement and professional growth.
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