Senior Low Power Digital Fault Tolerance Architect
7 days ago
We are seeking a skilled engineer to join our team in the development of ultra-low power semiconductor solutions. As a Staff Engineer, you will be responsible for designing and implementing low-power DFT architecture and infrastructure.
Your primary focus will be on scan insertion, boundary scan, MBIST, ATPG, and test time and test coverage analysis for scan and MBIST patterns.
You will work closely with designers on STA, physical, power, and logical issues related to DFT, as well as with test engineers to bring up test vectors on silicon.
This is an excellent opportunity for a motivated and self-driven engineer with attention to detail and strong verbal and written communication skills.
Required Skills and Qualifications- BS/MS in ECE/EE and at least 10 years of experience in DFT implementation
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan, and MBIST
- Experience in creating and implementing hierarchical DFT architecture in complex SoC
- Experience in Low-Power DFT and MBIST
- Experience in test time and test coverage analysis for scan and MBIST patterns
- Experience in working with test engineering team to bring up production test program
- Extensive knowledge of timing concepts and constraint development
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments
- Experience in RTL is required
- Experience in scripting like Tcl is preferred
- Experience with GLS (gate level simulation) is preferred
We offer a dynamic and fast-moving environment where you can work on complex, meaningful, and challenging projects that will create a lasting impact and shape the future of technology.
We encourage and nurture an environment for growth and opportunities to work with innovative and enthusiastic teams.
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