RTL Design Engineer

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm...

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

Roles & ResponsibilitiesResponsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of...

Roles & ResponsibilitiesResponsibilities: Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of...

Roles & ResponsibilitiesAs a Design Verification Manager, you are expected to carry out the following responsibilities.Be in-charge of a passionate verification team that is constantly pushing the limits Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system...

Roles & ResponsibilitiesAs a Design Verification Manager, you are expected to carry out the following responsibilities.Be in-charge of a passionate verification team that is constantly pushing the limits. Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system...

**Responsibilities**: - Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) - Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation - Verify Logic at ISP level and Digital System level - Optimize Design for less gate count...

**Job descriptions**: - Work on SoC/Subsystem define and integration. - Work on IP developments, Perform Verilog/System Verilog RTL design to meet product specifications and requirements； - Work with SW Engineer and HW Engineer on all aspect of SoC to optimise Silicon and board level design; - Work on SoC system block development, e.g., power management,...

**Responsibilities**: - Draw, update, and maintain designs - Manage multiple complex projects at the same time - Ensure our designs meet manufacturing, technical and customer Responsibilities - Ensure that all design projects are completed within budget and time **Qualifications**: - Bachelor's Degree or equivalent experience in Mechanical Engineering or...