Isp Rtl Design Engineer

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate count and low power consumption Drive ISP Design activities in close collaboration with ISP Algorithm...

**Responsibilities**: - Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) - Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation - Verify Logic at ISP level and Digital System level - Optimize Design for less gate count...

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

Roles & ResponsibilitiesResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital System level Optimize Design for...

**Responsibilities**: - Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) - Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation - Verify Logic at ISP level and Digital System level - Optimize Design for less gate count...

Roles & ResponsibilitiesResponsibilities:Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

**Job descriptions**: - Work on SoC/Subsystem define and integration. - Work on IP developments, Perform Verilog/System Verilog RTL design to meet product specifications and requirements； - Work with SW Engineer and HW Engineer on all aspect of SoC to optimise Silicon and board level design; - Work on SoC system block development, e.g., power management,...

**Responsibilities**: - Develop design requirements of an NPU given system level specifications. - Being part of modelling the performance of the NPU module and its data transaction throughput. - Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. - Understanding the mathematics of different...

**Description**: - You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical...

Roles & ResponsibilitiesResponsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of...