Senior Staff ASIC Physical Design Engineer

ResponsibilitiesAdvanced low-power physical design/integration flow developmentSynthesis, floor planning and place & routeFull-chip floor planning and layoutPower network design and analysisSupport signoff timing closure, power integrity, and signal integrityPhysical Verification using DRC, LVSQualificationsDegree or related field required3+ years industry...

Roles & Responsibilities Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or in-memory computing products. Handle IP integration and validation and support post-Si...

Responsible for RTL design, simulation, and verification for ASIC/SoC products.Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team.Create reusable internal IPs for AI and/or in-memory computing products.Handle IP integration and validation and support post-Si testing and...

Roles & Responsibilities Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Build reusable testbench, constrained-random/directed test cases, and...

Roles & ResponsibilitiesJob Description Working on 6nm and below advanced process project APR and Timing/PI sign-off Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros) Take the Block or Block coordinator role for complex blocks Do early prediction for critical APR/Timing/PI issuesJob Requirements ...

This will be a permanent position based in Jurong East There are 4 open positions: SoC Architecture Scope of Work Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Work on SoC floorplan with architect and APR; SoC...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Roles & ResponsibilitiesRESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO:• Develop microarchitecture and RTL design and verification for Expedera AI accelerators• Explore microarchitecture and architecture for design space optimization (power/performance/area)• Collaborate with HW/SW architects in HW specification process, HW/SW co-design• Execute...

Roles & ResponsibilitiesJOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure...

Roles & ResponsibilitiesJob OverviewIn today's information-centric world, the core of information technology lies in the semiconductor industry. UMC is a leading global semiconductor foundry company and we are sincerely inviting process engineers to join us. You have the opportunity to develop your expertise in the semiconductor industry and improve the...

Responsibilities:Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

JOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure successful tapeout, active...

Roles & ResponsibilitiesJOB DESCRIPTION· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support;...

JOB DESCRIPTION. Work on SoC architecture discussion and optimization with architect SoC integration system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc. Work on SoC floorplan with architect and APR SoC power check SoC timing constraints and review support SoC DFT support SoC verification plan and SoC...

Roles & ResponsibilitiesJob Description: Responsible for IP level and/or SOC level verification. Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios. Create verification environment/testbench with Bus Functional Model (BFM) using SystemVerilog,...

Roles & ResponsibilitiesKey responsibilities: Perform IC design of FTDI products Perform Verilog RTL design to meet product specifications and requirements Perform front-end verification using UV methodology Work with Systems and Software engineers on FPGA verification Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan...

Roles & ResponsibilitiesResponsibilities: Working on IC physical design of 12nm/7nm/6nm/5nm and below advanced process chip, from RTL to GDS. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff. Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block...

Roles & ResponsibilitiesCompany OverviewThe team has more than 15 years of experience developing 1G/2.5G/5GBase-T Ethernet physical layer PHY and switch chips for data centers, enterprise networks, and gateways and has sucessfully developed multiple generations of the most competitive products.The company is headquarted in Kunshan, and the R&D team is...

Roles & ResponsibilitiesResponsibilities: Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the...